Pei-Wen Li received
the Bachelor degree in Electrophysics from
Dr. Li’s
main research theme focuses on experimental silicon-germanium nanostructures
and devices. Her present research encompasses germanium quantum dot single
electron transistors, photodetectors, nonvolatile memory, and energy saving (photovoltaic
and thermoelectric) devices, making use of self-assembly nanostructures in
silicon integration technology. Her research group has successfully developed a
novel CMOS-compatible, self-organized approach for the generation of germanium
quantum dots on Si-containing layers through thermal oxidation of
silicon-germanium-on-insulator structures. Of particular, the successful
demonstration of precise placement and size control of the self-assembled germanium
quantum dots shed a light on the practical
creation of new nano-electronic, nano-photonic, and electromechanical devices.
She has produced the first Ge
quantum-dot single electron transistor with self-aligned nanoelectrodes that produces
room-temperature Coulomb blockade characteristics with very large
peak-to-valley ratio up to 750 and excellent Coulomb stability (“Fabrication of a germanium quantum-dot single electron transistor
with large Coulomb-blockade oscillations at room temperatures,” Applied Physics
Letters, vol. 85, p. 1532. (cited time: 38), and “Tunneling spectroscopy of
germanium quantum-dot in single-hole transistors with self-aligned electrodes,”
Nanotechnology, vol. 18, p. 475402).
She has also successfully demonstrated wavelength-tunable from near
ultraviolet (NUV) to near infrared (NIR) Ge quantum-dot photodetectior in 2012
(“CMOS-compatible generation of self-organized 3D Ge quantum dot array for photonic
and thermoelectric applications,” IEEE Trans. Nanotechnology, vol. 11, no. 4,
p. 657-660.).
Dr. Li has published more than 60
Journal papers and holds 4 patents in Si device
processing.
Y. Ho, M. Cheng, P. W. Li, H. Cheng,
U. Huang, and S. Wu, “Method of
Manufacturing a Crown Shape Capacitor”, USA patent 5,932,115,
M. J. Cherng and
P. W. Li, “Method for Etching Polymer-Assisted Reduced Small Contacts
for Ultra Large Scale Integration Semiconductor Devices, “ USA patent
5,719,089,
M. J. Cherng and
P. W. Li, “Method for Etching Polymer-Assisted Reduced Small Contacts
for Ultra Large Scale Integration Semiconductor Devices, “ ROC patent 090820,
Y. Ho, M. J.
Cherng, and P. W. Li, “Method for Etching-Assisted Technique for
Capacitor Fabrication,” ROC patent 082555,
Dr. Li was awarded Distinguished Young Electrical Engineer from Chinese Electrical
Engineering Society in 2005, Distinguished Professorship from National
Central University in
2006-2013, Top 10 Rising Stars in Taiwan (Science and
Technology) from Central News Agency in 2008.
Dr. Li has supervised 10 PhD
students and more than 45 Master students.